We are seeking a Verification engineer who will be responsible for performing ASIC Verification based on architectural or micro-architectural specification review and analysis followed with definition of Verification requirements. for a long term contract assignment in Santa Clara, CA.
Our client is a leading global manufacturer of electronic semiconductor products that meet a variety of needs within the Commercial, Home, Intelligence, and Advanced Technology computing industries.
We at Ian Martin envision a world where everyone is connected in meaningful work and if you find great meaning in developing some of the most widely used products in the world, then we have the career path for you.
On a day to day basis your work will include:
- RTL design verification with SystemVerilog and UVM
- Knowledge and understanding of networking protocols, layer 2 and layer 3
- Knowledge and understanding of high speed Ethernet protocols (25G/50G/100G/400G), including
- MAC and PCS layers; in-depth knowledge of FEC, scramble/descramble and lane alignment techniques preferred
- Strong Knowledge of possible Serdes and MAC related errors
- Strong logical and problem solving skills
- Experience in Synopsys Ethernet VIP preferred
Applicants with Bachelors Degree or higher and Strong debug abilities will be contacted by our team for a deeper level discussion about this role.
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We value diversity and inclusion and encourage all qualified people to apply. If we can make this easier through accommodation in the recruitment process, please contact us at email@example.com. We encourage all qualified candidates to apply; however, only those selected for an interview will be contacted.